NXP Semiconductors /LPC43xx /SPIFI /CMD

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Interpret as CMD

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DATALEN0 (POLL)POLL 0 (INPUT_FROM_SERIAL_FL)DOUT 0INTLEN 0 (ALL_SERIAL)FIELDFORM 0 (RESERVED)FRAMEFORM 0OPCODE

DOUT=INPUT_FROM_SERIAL_FL, FIELDFORM=ALL_SERIAL, FRAMEFORM=RESERVED

Description

SPIFI command register

Fields

DATALEN

Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field.

POLL

This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs

DOUT

If the DATALEN field is not zero, this bit controls the direction of the data:

0 (INPUT_FROM_SERIAL_FL): Input from serial flash.

1 (OUTPUT_TO_SERIAL_FLA): Output to serial flash.

INTLEN

This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes.

FIELDFORM

This field controls how the fields of the command are sent.

0 (ALL_SERIAL): All serial. All fields of the command are serial.

1 (QUADDUAL_DATA): Quad/dual data. Data field is quad/dual, other fields are serial.

2 (SERIAL_OPCODE): Serial opcode. Opcode field is serial. Other fields are quad/dual.

3 (ALL_QUADDUAL): All quad/dual. All fields of the command are in quad/dual format.

FRAMEFORM

This field controls the opcode and address fields.

0 (RESERVED): Reserved.

1 (OPCODE): Opcode. Opcode only, no address.

2 (OPCODE_ONE_BYTE): Opcode one byte. Opcode, least significant byte of address.

3 (OPCODE_TWO_BYTES): Opcode two bytes. Opcode, two least significant bytes of address.

4 (OPCODE_THREE_BYTES): Opcode three bytes. Opcode, three least significant bytes of address.

5 (OPCODE_FOUR_BYTES): Opcode four bytes. Opcode, 4 bytes of address.

6 (NO_OPCODE_THREE_BYTE): No opcode three bytes. No opcode, 3 least significant bytes of address.

7 (NO_OPCODE_FOUR_BYTES): No opcode four bytes. No opcode, 4 bytes of address.

OPCODE

The opcode of the command (not used for some FRAMEFORM values).

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